EDA程序改错题

实用文档 程序改错题程序改错题 1.已知 sel 为 STD_LOGIC_VECTOR(1DOWNTO 0)类型的信号，而 a、b、c、d、q 均为 STD_LOGIC 类型的信号，请判断下面给出的CASE 语句程序片段： CASE sel IS WHEN“00”=qqqq null; end case; end process;end process; end one; 4 4、、LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY counter IS PORT ( reset: IN STD_LOGIC; clock: IN STD_LOGIC; num: buffer integer range 0 to 3； 多一个“；多一个“；” ); END; ARCHITECTURE behav OF jishu IS jishujishu 改为改为 counter counter Begin Process(reset,clock) 标准文案 实用文档 Begin If reset=’1’ then num=0; Elsif rising_edge(clock) then If num=3 then num=0; else num=num+1; 少少 end if;end if; end if; end process; end; 5 5、、LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED;STD_LOGIC_UNSIGNED.ALL ENTITY LX3_2 IS PORT(CLK,CLR,OE:IN BIT; D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END LX3_2; ARCHITECTURE struc OF LX3_2 IS VARIABLE Q_TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL BEGIN PROCESS(CLR)PROCESS(CLK) BEGIN 标准文案 实用文档 IF CLR= 0 THEN Q_TEMP= 00000000 ;“00000000“ ELSIF CLK= 1 THEN Q_TEMP=D; ELSE Q_TEMP=Q_TEMP; END IF; END PROCESS; Q=Q_TEMP WHEN OE= 1 ELSE “ZZZZZZZZ“; END struc; 6 6、、LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LX3_2 IS PORT( A :IN STD_LOGIC_VECTOR(3 DOWNTO 0); B :IN STD_LOGIC(3 DOWNTO 0);STD_LOGIC_VECTOR GT,LT,EQ: OUT STD_LOGIC); END LX3_2; ARCHITECTURE one OF LX8_2 ISLX3_2 BEGIN PROCESS(A,B) BEGIN GT= 0 ; LT= 0 ; EQB THEN GT=”0”; 0 ELSIF AB THEN LT=”0”; 0 ELSE EQ null; 附：自动化 123江西理工大学王显聪 标准文案 实用文档 标准文案