300mA的超低噪声小封装超高速CMOSLDO稳压器LP3984

Preliminary DatasheetPreliminary DatasheetLP3984LP3984 300mA,Ultra-low noise, Small Package300mA,Ultra-low noise, Small Package Ultra-Fast CMOS LDO RegulatorUltra-Fast CMOS LDO Regulator General DescriptionGeneral Description The LP3984 is designed for portable RF and wireless applications with demanding perance and space requirements. The LP3984 perance is optimized for battery-powered systems to deliver ultra low noise and low quiescent current. A noise bypass pin is availableforfurtherreductionofoutputnoise. Regulator ground current increases only slightly in dropout,furtherprolongingthebatterylife.The LP3984 also works with low-ESR ceramic capacitors, reducing the amount of board space necessary for powerapplications, critical inhand-heldwireless devices. The LP3984 consumes less than 0.01µA in shutdown mode and has fast turn-on time less than 50µs. The other features include ultra low dropout voltage,highoutputaccuracy,currentlimiting protection, and high ripple rejection ratio. It is available in the 5-lead of SOT23-5 packages. 30:3.0V 33:3.3V FeaturesFeatures Ultra-Low-Noise for RF Application 2V- 6.5V Voltage Range Low Dropout : 200mV @ 300mA 1.2V, 1.3V,1.5V, 1.8V, 2.5V, 2.8V 3.0V and 3.3V Fixed 300mA Output Current, 550mA Peak Current High PSSR:-73dB at 1KHz 2.5V RLOAD = 1Ω VEN ≥ 1.2V, IOUT = 0mA IOUT = 200mA, VOUT Dropout VoltageVDROP 2.8V IOUT = 300mA, VOUT 2.8V Line Regulation Load Regulation Standby Current EN Bias Current Logic-Low EN Threshold Voltage Logic-High Voltage Output Noise Voltage Power Supply Rejection Rate VIH f = 100HzPSRR f = 10kHz ΔVLINE ΔLOAD ISTBY IIBSD VIL VIN = (VOUT + 1V) to 5.5V, IOUT = 1mA 1mA 25mΩ on the LP3984 output ensures stability. The LP3984 still works well with output capacitor of other types due to the wide stable ESR range. Figure 1 shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the LP3984 and returned to a clean analog ground. the voltage on the EN pin falls below 0.4 volts. For to protectingthesystem,theLP3984havea quick-discharge function. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. Bypass Capacitor and Low NoiseBypass Capacitor and Low Noise Connecting a 22nF between the BP pin and GND pin significantly reduces noise on the regulator output, it is critical that the capacitor connection between the BP pin and GND pin be direct and PCB traces should be as short as possible. There is a relationship between the bypass capacitor value and the LDO regulator turn on time. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation perance. Thermal ConsiderationsThermal Considerations Thermal prot