超大规模集成电路第六次作业2016秋,段成华

1. The following figure shows a C2MOS based dual-edge triggered register. Its advantage is that a lower frequency clock (half of the original rate) is distributed for the same functional throughput, resulting in power savings in the clock distribution network. (1)Calculate the timing parameters of setup timetSU, hold time tH and propagation delaytCO of the register with respect to the rising edge of the clockCLK, given that the inverter delay is tINV. (2)Assume that the transistors are with the minimum size and C = 20 fF. Verify the function of the dual-edge triggered register and itstiming parameters in (1) by using HSPICE and TSMC 0.18 um CMOS technology model with 1.8 V power supply. (3)Determine respectively the maximum work frequency fmaxof the register by HSPICE simulation. (4)Determine the maximum fresh cycle of the register. Solution: （1）、 C2MOS 电路对时钟重叠不敏感所以 CLK 和 CLK’因反相器导致的延时问题不予考虑。CLK 在上升沿之前为低电平，假设输入 D 为 1，M9，M10 和 M1 导通，则 Y 为 0，所以 tSU=tINV（类似反相器的传播延时）+tINV（CLK 到 CLK’ 反相器导致的延时） =2 tINV；由于上升沿到来后 CLK 为高电平， M9 和 M10 关断，所以在时钟变为高电平后输入的任何变化都不会影响输出，所以 tH=0；当 CLK 上升沿到来，则 M14， M13 和 M12 导通 Y=0 反向输出到 Q （为 1），所以 tCO= tINV （类似反相器的传播延时）+tINV（CLK 到 CLK’反相器导致的延时）=2 tINV。可以看出 C2MOS 电路相比于静态电路延时很小。（2）、代码如下： .title C2MOS LOGIC OF INVERTERS .lib C:\synopsys\Hspice_D-2010.03-SP1\tsmc018\mm018.l TT * set 0.18um library .options post=2 list .temp 27 .global vdd Vdd vdd gnd 1.8 vclkn vclkn 0 0.9 pulse 0.0 1.8 1500p 5p 5p 2990p 6000p vinvin 0 0.9 PWL 0p 0,1280p 0,1285p 1.8 C1 voutx gnd 20f C2 vouty gnd 20f C3 vqgnd 20f .subcktPN-TYPE-INV1 clkn clkp D out n2 n1 wn=0.35u wp=1.0u t=0.5u m1 n2 D gnd gnd NCH l=0.2u w=wn ad= wn*t pd= wn+2*t as= wn*t ps= wn+2*t m2 out clkn n2 gnd NCH l=0.2u w=wn ad= wn*t pd= wn+2*t as= wn*t ps= wn+2*t m3out clkp n1 vdd PCH l=0.2u w=wp ad= wp*t pd= wp+2*t as= wp*t ps= wp+2*t m4 n1D vdd vdd PCH l=0.2u w=wp ad= wp*t pd= wp+2*t as= wp*t ps= wp+2*t .ends .subcktPN-TYPE-INV2 clkn clkp D out wn=0.35u wp=1.0u t=0.5u m1 n2 D gnd gnd NCH l=0.2u w=wn ad= wn*t pd= wn+2*t as= wn*t ps= wn+2*t m2 outclkn n2 gnd NCH l=0.2u w=wn ad= wn*t pd= wn+2*t as= wn*t ps= wn+2*t m3 out clkp n1 vdd PCH l=0.2u w=wp ad= wp*t pd= wp+2*t as= wp*t ps= wp+2*t m4 n1 D vdd vdd PCH l=0.2u w=wp ad= wp*t pd= wp+2*t as= wp*t ps= wp+2*t .ends .subcktPN-TYPE-tINV clkp clkn out n2 n1 wn=0.35u wp=1.0u t=0.5u m1 out clkp n2 gnd NCH l=0.2u w=wn ad= wn*t pd= wn+2*t as= wn*t ps= wn+2*t m2 out clkn n1 vdd PCH l=0.2u w=wp ad= wp*t pd= wp+2*t as= wp*t ps= wp+2*t .ends .subckt inv in out wn=0.35u wp=1.0u t=0.5u m1 out in gnd gnd NCH l=0.2u w=wn ad= wn*t pd= wn+2*t as= wn*t ps= wn+2*t m2 out in vdd vdd PCH l=0.2u w=wp ad= wp*t pd= wp+2*t as= wp*t ps= wp+2*t .ends X1 vclkn vclkpinv X2 vclkn vclkp vinvoutx n2 n1 PN-TYPE-INV1 X3 vclkp vclkn voutx vqPN-TYPE-INV2 X4 vclkp vclkn vouty n2 n1PN-TYPE-tINV X5 vclkn vclkp vouty vqPN-TYPE-INV2 .op .tran 5p 18000p .meas tran vqmax max v(vq) from=50p to=18000p .meas tran vqmin min v(vq) from=5