综合脚本

script for Design Compiler Language TCL Usage 1 make sure the lib in the current directory 2 if you have the file .synopsys_dc.setup, set synopsys_dc_setup_file 1, if not, set synopsys_dc_setup_file 0 3 change Step 3 Variables to what you want Especially top module name, clock name, reset name, all files name, and period 4 typing dc_shell-t -f run_72.tcl | tee -i run.log set synopsys_dc_setup_file 0 ----------------------------------------------------- Step 1 Setting Up path and library If you have edited the file .synopsys_dc.setup, then you can skip over this step ----------------------------------------------------- if { synopsys_dc_setup_file 0} { set search_path [list /home/chanshi/dc/library/smic /home/chanshi/dc/rfid/source /home/chanshi/dc/script] set target_library {typical.db} set target_library {CSM35OS142_typ.db}; if you want use typical library,change to typical.db set link_library [list {*} ram_interp_typical_syn.db ram_458_typical_syn.db typical.db] set link_library [list {*} target_library] } set symbol_library {csm18ic.sdb csm18io.sdb} set synthetic_library {dw_foundation.sldb}; Design Ware set command_log_file“command.log“ ----------------------------------------------------- Step 2 Compile Swithes ----------------------------------------------------- set verilogout_no_tritrue ; if inout used, tri net will be used 通过将三态（tri）逻辑声明成线网（wire）来确保网表中不会出现三态逻辑，因为一些布 线工具很难读取包含 tri、tran 源语、assign 语句的网表，对于“inout”类型的 port,DC 产生 tri wire 语句和 tran 源语，对于 tri，还会产生 assign 语句 set test_default_scan_stylemultipld_flip_flop 设置扫描链的类型，还可以通过set_scan_configuration -style来设置 set link_force_casecase_insensitive 设置 link 命令是否区分大小写，默认是check_reference,就是根据产生 reference 的模块 格式来判断是否大小写敏感，如果是vhdl 格式就是不敏感，如果是verilog 就敏感 define_name_rules VLSI_NET -allowed “a-zA-Z0-9_“ -first_restricted “0-9_“ -type net -max_length 256 define_name_rules VLSI_CELL -allowed “a-zA-Z0-9_“ -first_restricted “0-9_“ -type cell -max_length 256 define_name_rules VLSI_PORT -allowed “a-zA-Z0-9_“ -first_restricted “0-9_“ -type port -max_length 256 define_name_rules TAN_RULE -allowed “a-zA-Z0-9_“ -first_restricted “0-9_\[]“ -max_length 256 -map {{{“*cell*“, “mycell“}, {“*-return“, “myreturn“}}}; set hdlin_check_no_latch “true“ 设置如果推断出锁存器，是否报warning，默认是 false，即不报。 set hdlin_merge_nested_conditional_statements “true“ 顾名思义，是否把嵌套的if 融合，默认值是 false，就是对于嵌套的条件语句（if 或 case 语句）中的每一个if 和 case 都推断出一个选择器，这种做法有利于把某些迟到的条件判断 信号（late arriving signals）安排到离输出最近的选择器上（进而有利于减小延迟），如果 设成 true， 就会把这些选择器融合成一个大的选择器， 这样所有的选择信号到输出的距离都 是相同的 ----------------------------------------------------- Step 3 Define Variables ----------------------------------------------------- set active_design “whole_modules“; Top module name source files.tcl; All RTL source_files verilog set clock_name “clk“; Name of clock set reset_name “reset“; Name of reset set clk_period 70.0 设置时钟周期，注意带小数点，这样计算出的值都带